In fields of display devices that display images, plasma display devices using plasma display panels (hereinafter abbreviated as PDPs) have the advantages that thinning and larger screens are possible. In the plasma display devices, images are displayed utilizing light emission in cases where discharge cells composing pixels are discharged.
The plasma display devices are roughly classified into AC type and DC type plasma display devices depending on driving forms.
FIG. 29 is a block diagram showing the basic configuration of a conventional AC-type plasma display device.
A plasma display device 900 shown in FIG. 29 comprises an analog-to-digital converter (hereinafter referred to as an A/D converter) 910, a video signal/sub-field corresponder 920, a sub-field processor 930, a data driver 940, a scan, river 950, a sustain driver 960, and a PDP 970.
An analog video signal VD is fed to the A/D converter 910. The A/D converter 910 converts the video signal VD into digital image data, and feeds the digital image data into the video signal/sub-field corresponder 920. Since the video signal/sub-field corresponder 920 divides one field into a plurality of sub-fields to perform display, image data SP corresponding to each of the sub-fields is generated from image data corresponding to one field, and is fed to the sub-field processor 930.
The sub-field processor 930 generates a data driver driving control signal DS, a scan driver driving control signal CS, and a sustain driver driving control signal US from the image data SP for each sub-field, and respectively feeds the signals to the data driver 940, the scan driver 950, and the sustain driver 960.
The PDP 970 comprises a plurality of address electrodes (data electrodes) 911, a plurality of scan electrodes 912, and a plurality of sustain electrodes 913. The plurality of address electrodes 911 are arranged in the vertical direction on a screen, and the plurality of scan electrodes 912 and the plurality of sustain electrodes 913 are arranged in the horizontal direction on the screen. The plurality of sustain electrodes 913 are commonly connected to one another.
A discharge cell is formed at each of intersections of the address electrodes 911, the scan electrodes 912, and the sustain electrodes 913. Each of the discharge cells 914 composes a pixel on the screen.
The data driver 940 is connected to the plurality of address electrodes 911 in the PDP 970. The scan driver 950 contains a drive circuit provided for each of the scan electrodes 912, and each of the drive circuits is connected to the corresponding scan electrode 912 in the PDP 970. The sustain driver 960 is connected to the plurality of sustain electrodes 913 in the PDP 970.
The data driver 940 applies a data pulse to the corresponding address electrode 911 in the PDP 970 in response to the image data SP in a write time period in accordance with the data driver driving control signal DS. The scan driver 950 successively applies a write pulse to the plurality of scan electrodes 912 in the PDP 970 while shifting a shift pulse in a vertical scanning direction in the write time period in accordance with the scan driver driving control signal CS. Consequently, address discharges are induced in the corresponding discharge cell 914.
The scan driver 950 applies a periodical sustain pulse to the plurality of scan electrodes 912 in the PDP 970 in a sustain time period in accordance with the scan driver driving control signal CS. On the other hand, the sustain driver 960 simultaneously applies a sustain pulse whose phase is shifted by 180 degrees from the sustain pulse in the scan electrode 912 to the plurality of sustain electrodes 913 in the PDP 970. Consequently, sustain discharges are induced in the corresponding discharge cell 914.
FIG. 30 is a timing chart showing an example of respective driving voltages of the address electrodes, the scan electrodes, and the sustain electrodes in the PDP 7 shown in FIG. 29.
In an initialization time period, an initial setup pulse Pset is simultaneously applied to the plurality of scan electrodes 912. Thereafter, in a write time period, a data pulse Pda that is turned on or off in response to a video signal is applied to each of the address electrodes 911, and a write pulse Pw is successively applied to the plurality of scan electrodes 912 in synchronization with the data pulse Pda. Thus, address discharges are successively induced in the selected discharge cells 914 in the PDP 970.
In a sustain time period, a sustain pulse Psc is periodically applied to the plurality of scan electrodes 912, and a sustain pulse Psu is periodically applied to the plurality of sustain electrodes 913. The phase of the sustain pulse Psu is shifted by 180 degrees from the phase of the sustain pulse Psc. Consequently, sustain discharges are induced subsequently to the address discharges.
In such a plasma display device, an increase in the number of discharge cells 14 (an increase in the number of pixels) with larger screens and higher precision has been significant in recent years. A peak current value of an address discharge current flowing on one of the scan electrodes 912 at the time of address discharges may, in some cases, be increased by the increase in the number of discharge cells 14. When the peak current value of the address discharge current is increased, a large voltage drop is produced in the write pulse Pw applied to the scan electrode 912. As a result, address discharges become unstable. In order to induce stable address discharges, therefore, a voltage SH2 of the write pulse Pw to be applied to the scan electrode 912 must be set to a high voltage.
On the other hand, as a method of reducing the peak current value of the address discharge current, a method of driving a plasma display panel for giving a phase difference to the data pulse Pda to be applied to the address electrode between a plurality of data drivers divided from the data driver 940 shown in FIG. 29 has been proposed (see JP 08-305319 A, for example)
The method of driving the plasma display panel will be described.
FIG. 31 is a schematic view showing an example of the display state of a PDP 970 in a plasma display device composed of a plurality of data drivers obtained by the division, and FIG. 32 is a diagram for explaining dependency of an address discharge current on a data pulse phase difference. The data pulse phase difference will be described later.
In FIG. 31, first and second data drivers 940a and 940b are connected to the sub-field processor 930 shown in FIG. 29. The PDP 970 has the same configuration as that of the PDP 970 shown in FIG. 29 except that it comprises a plurality of address electrodes 911a and 911b. 
A shift TR between timing at which the first data driver 940a applies the data pulse Pda shown in FIG. 30 to the address electrode 911a and timing at which the second data driver 940b applies the data pulse Pda shown in FIG. 30 to the address electrode 911b will be described while referring to FIG. 32.
In the following description, the timings at which the first and second data drivers 940a and 940b respectively apply the data pulse Pda to the address electrodes 911a and 911b will be referred to as timing of data pulse application. Further, the shift TR between the timing of data pulse application to the address electrode 911a and the timing of data pulse application to the address electrode 911b will be referred to as a data pulse phase difference TR.
In FIG. 31, all the discharge cells 914 on a scan electrode 912f on the first line from above out of the discharge cells 914 on the PDP 970 are light-emitted.
A case where the discharge cell 914 on the scan electrode 912f on the first line from above is light-emitted is assumed. In a case where the data pulse phase difference TR does not exist, as shown in FIG. 32(a). The discharge cell 914 on the address electrode 911a and the discharge cell 914 on the address electrode 911b respectively induce address discharges at the same timing t1. Thus, a discharge current DA2 having one peak is generated in the scan electrode 912f. 
In this case, respective discharge currents of the discharge cell 914 on the address electrode 911a and the discharge cell 914 on the address electrode 911b simultaneously flow through the scan electrode 912f, so that the amplitude AM2 of the discharge current DA2 increases. Consequently, a large voltage drop E2 is produced in a write pulse Pw applied to the scan electrode 912f. As a result, address discharges become unstable, as described above.
On the other hand, in a case where the data pulse phase difference TR exists, as shown in FIG. 32(b), the discharge cell 914 on the address electrode 911a induces address discharges at the timing t1, and the discharge cell 914 on the address electrode 911b induces address discharges at the timing t2. Thus, a discharge current DA1 having two peaks is generated in the scan electrode 912f. 
In this case, respective discharge currents of the discharge cell 914 on the address electrode 911a and the discharge cell 914 on the address electrode 911b respectively flow through the scan electrode 912f at the different timings t1 and t2, so that the amplitude AM1 of the discharge current DA1 decreases as the data pulse phase difference TR increases. Thus, a voltage drop E1 produced in the write pulse Pw applied to the scan electrode 912f also decreases as the data pulse phase difference TR increases. Even in a case where a voltage SH1 of the write pulse Pw to be applied to the scan electrode 912f is set to a low voltage, stable discharges can be ensured. In other words, the data pulse phase difference TR is set to a large value, so that a voltage (a driving voltage) of the write pulse Pw can be reduced while ensuring stable discharges of the discharge cell 914.
Meanwhile, in the plasma display device 900 shown in FIG. 29, the plurality of discharge cells 914 in the PDF 970 have the function of a capacitor. The capacitance of the plurality of discharge cells 914 in the PDF 970 is hereinafter referred to as a panel capacitance.
In the above-mentioned write time period, a circuit loss (power loss) in the data driver 940 in a case where the data pulse Pda is applied to each of the address electrodes 911 is proportional to the product of the panel capacitance and the square of the driving voltage applied to each of the address electrodes 911. This relationship is expressed by the following equation:P∝Cp×Vp2   (1)
In the foregoing equation (1), P denotes a circuit loss, Cp denotes a panel capacitance, and Vp denotes a driving voltage. In this case, the driving voltage Vp is a voltage of the data pulse Pda.
Consequently, power consumption in the entire plasma display device 900 in the write time period increases as the PDP 970 increases in size (the panel capacitance increases) and the driving voltage is raised. Therefore, a power recovery circuit is developed in order to reduce the power consumption in the plasma display device 900 (reduce the circuit loss).
FIG. 33 is a circuit diagram showing an example of a conventional power recovery circuit. In FIG. 33, a power recovery circuit 980 is connected to a data driver integration circuit contained in the data driver 940 shown in FIG. 29. Further, the data driver integration circuit is connected to the plurality of address electrodes 911 in the PDP 970.
In FIG. 33, the capacitances of a plurality of discharge cells 914 formed of the address electrodes 911 are respectively taken as address electrode capacitances Cp1 to Cpn, and the sum is represented as a panel capacitance Cp.
The power recovery circuit 980 comprises a recovery capacitor C1, a recovery coil L, N-channel field effect transistors (hereinafter abbreviated as transistors) Q1 to Q4, and diodes D1 and D2.
The recovery capacitor C1 is connected between a node N3 and a ground terminal. The transistor Q4 and the diode D2 are connected in series between the node N3 and a node N2, and the diode D1 and the transistor Q3 are connected in series between the node N2 and the node N3.
The recovery coil L is connected between the node N2 and a node N1. The transistor Q1 is connected between the node N1 and a power supply terminal V1, and the transistor Q2 is connected between the node N1 and the ground terminal.
A power supply voltage Vda is applied to the power supply terminal V1. Control signals S1 to S4 are respectively fed to the gates of the transistors Q1 to Q4. The transistors Q1 to Q4 respectively perform an ON/OFF switching operation on the basis of the control signals S1 to S4.
FIG. 34 is a timing chart showing the operations in a write time period of the power recovery circuit 980 shown in FIG. 33. FIG. 34 shows the respective waveforms of a voltage NV1 at the node N1 shown in FIG. 33 and the control signals S1 to S4 respectively applied to the transistors Q1 to Q4. The transistors Q1 to Q4 are turned on when the control signals S1 to S4 are at a high level, while being turned off when the control signals S1 to S4 are at a low level.
In a time period TA, the control signal S3 is at a high level, and the control signals S1, S2, and S4 are at a low level. Consequently, the transistor Q3 is turned on, and the transistors Q1, Q2, and Q4 are turned off. In this case, the recovery capacitor C1 is connected to the recovery coil L through the transistor Q3 and the diode D1, and the voltage NV1 at the node N1 is gently raised due to LC resonance of the recovery coil L and the panel capacitance Cp. At this time, charges in the recovery capacitor C1 are discharged into the panel capacitance Cp through the transistor Q3, the diode D1, and the recovery coil L.
In a time period TB, the control signal S1 is at a high level, and the control signals S2 to S4 are at a low level. Consequently, the transistor Q1 is turned on, and the transistors Q2 to Q4 are turned off. In this case, the voltage NV1 at the node N1 is rapidly raised and is fixed to a power supply voltage Vda.
In a time period TC, the control signal S4 is at a high level, and the control signals S1 to S3 are at a low level. Consequently, the transistor Q4 is turned on, and the transistors Q1 to Q3 are turned off. In this case, the recovery capacitor C1 is connected to the recovery coil L through the diode D2 and the transistor Q4, and the voltage NV1 at the node N1 is gently lowered due to LC resonance of the recovery coil L and the panel capacitance Cp. At this time, charges stored in the panel capacitance Cp are stored in the recovery capacitor C1 through the recovery coil L, the diode D2, and the transistor Q4. Consequently, power is recovered.
In a time period TD, the control signal S2 is at a high level, and the control signals S1, S3, and S4 are at a low level. Consequently, the transistor Q2 is turned on, and the transistors Q1, Q3, and Q4 are turned off. In this case, the node N1 is connected to the ground terminal, and the voltage NV1 at the node N1 is rapidly lowered and is fixed to a ground potential.
Thus, the power recovery circuit 980 causes the charges stored in the panel capacitance Cp to be recovered in the recovery capacitor C1 and causes the recovered charges to be fed to the panel capacitance Cp again. Power based on the charges recovered in the recovery capacitor C1 by the panel capacitance Cp is referred to as recovery power.
Consequently, the above-mentioned circuit loss can be reduced, so that the power consumption in the whole plasma display device 900 can be reduced. In FIG. 34, a voltage change indicated by an arrow RQ corresponds to the recovery power, and a voltage change indicated by an arrow LQ corresponds to the circuit loss.
According to the power recovery circuit 980, however, sufficient power recovery is not necessarily made. The reason for this will be described on the basis of FIGS. 35 and 36.
FIG. 35 is a schematic view showing an example of the display state of the PDP 7, and FIG. 36 is a waveform diagram of the data pulse applied to the address electrodes in order to obtain the display state shown in FIG. 35. In FIG. 35, only a part of the PDP 970 shown in FIG. 29 is illustrated.
FIG. 35(a) illustrates an example in which four pixels (discharge cells) provided in each of the address electrodes 911 display “black”, “white”, “black”, and “black” in this order from above. That is, the example is an example in which only the pixel (discharge cell) on the second line from above in the PDF 970 induces address discharges.
When the power recovery circuit 980 shown in FIG. 33 is not used, the data pulse Pda is generated by power supplied from a power supply. An example of the waveform of the data pulse Pda in this case is illustrated in FIG. 36(a). In FIG. 36(a), a voltage change indicated by an arrow LQ corresponds to a circuit loss.
When the power recovery circuit 980 is used, the data pulse Pda is generated by power supplied from the power supply and power recovered from the above-mentioned panel capacitance Cp. An example of the waveform of the data pulse Pda in this case is illustrated in FIG. 36(b). In FIG. 36(b), a voltage change indicated by an arrow LQ corresponds to a circuit loss, and a voltage change indicated by an arrow RQ corresponds to recovery power.
According to FIGS. 36(a) and 36(b), the power recovery circuit 980 is used, so that the circuit loss in the data driver 940 in a case where the data pulse Pda is generated is reduced by the recovery power from the panel capacitance Cp.
On the other hand, FIG. 35(b) illustrates an example in which four pixels provided in each of the address electrodes 911 display “white”, “white”, “white”, and “white” in this order from above. That is, the example is an example in which all the pixels on the PDP 970 induce address discharges. In this case, a plurality of data pulses Pda are continuously applied to each of the address electrodes 911.
Here, a case where the continuous data pulses Pda are applied as one set of data pulses SPd to each of the address electrodes 911 without using the power recovery circuit 980 is assumed.
An example of the waveforms of the data pulses Pda and SPa is illustrated in FIG. 36(c). In FIG. 36(c), an arrow LQ corresponds to a circuit loss. In this case, the circuit loss in the data driver 940 occurs when the data pulse SPda rises, while the circuit loss in the data driver 940 does not occur between the data pulses Pda.
A case where the continuous data pulses Pda are applied onto each of the address electrodes 911 using the power recovery circuit 980 is then assumed.
An example of the waveforms of the continuous data pulses Pda in this case is illustrated in FIG. 36(d). In FIG. 36(d), a voltage change indicated by an arrow LQ corresponds to a circuit loss, and a voltage change indicated by an arrow RQ corresponds to recovery power. When the power recovery circuit 980 is used, each of the continuous data pulses Pda is generated by power recovered from the panel capacitance Cp and power supplied from the power supply. Consequently, a circuit loss in the data driver 940 occurs every time each of the data pulses Pda rises.
The respective waveforms of the data pulses Pda shown in FIGS. 36(c) and 36(d) are compared with each other. In FIG. 36(c), a large circuit loss occurs one at a time when the data pulse SPda rises. On the other hand, in FIG. 36(d), a small circuit loss occurs one at a time when each of the data pulses Pda rises. When the number of data pulses Pda continuously generated is further increased, therefore, the circuit loss cannot be sufficiently reduced even if power is recovered by the power recovery circuit 980. In the conventional power recovery circuit 980, therefore, the circuit loss cannot, in some cases, be reduced.
JP 2002-156941 A discloses a driving method for reducing, when all pixels in the PDP 970 as shown in FIG. 35(b) induce address discharges, that is, a plurality of data pulses Pda are continuously applied to each of the address electrodes 911, a circuit loss by reducing the pulse amplitude of the data pulses Pda. However, further stabilization of address discharges and reduction of power consumption are required.